Analog Devices AD9912 Instrukcja Użytkownika

1 GSPS Direct Digital Synthesizer with 14-Bit DAC AD9912 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable.

AD9912 Rev. D | Page 10 of 40 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, AVDD3, and DVDD at nominal supply voltage; DAC RSET = 10 kΩ, unless otherw

AD9912 Rev. D | Page 11 of 40 06763-00919.85 19.95 20.05 20.15 20.25 20.35FREQUENCY (MHz)100–10–20–30–40–50–60–70–80–90–100–110SIGNAL POWER (dBm)2

AD9912 Rev. D | Page 12 of 40 06763-015100 1k 10k 100k 1M 10M 100MFREQUENCY OFFSET (Hz)–100–110–120–130–140–150PHASE NOISE (dBc/Hz)800MHz600MHzRMS

AD9912 Rev. D | Page 13 of 40 06763-051100 1k 10k 100k 1M 10M 100MFREQUENCY OFFSET (Hz)–125–115–135–145–155–165–175PHASE NOISE (dBc/Hz)RMS JITTER

AD9912 Rev. D | Page 14 of 40 06763-0210 200 400 600 800FREQUENCY (MHz)650600550500450AMPLITUDE (mV)NOM SKEW 25°C, 1.8V SUPPLYWORST CASE (SLOW SKE

AD9912 Rev. D | Page 15 of 40 INPUT/OUTPUT TERMINATION RECOMMENDATIONS DOWNSTREAMDEVICE(HIGH-Z)AD99121.8VHSTLOUTPUT100Ω06763-0270.01µF0.01µF Figu

AD9912 Rev. D | Page 16 of 40 THEORY OF OPERATION 06763-031DDS/DACFREQUENCYTUNING WORD÷S2×DIGITAL SYNTHESIS CORECONTROLLOGICLOW NOISECLOCKMULTIPLI

AD9912 Rev. D | Page 17 of 40 06763-032DAC(14-BIT)ANGLE TOAMPLITUDECONVERSION14191948484814PHASEOFFSETQD48-BIT ACCUMULATORFREQUENCYTUNING WORD(FTW

AD9912 Rev. D | Page 18 of 40 PRIMARYSIGNALFILTERRESPONSESIN(x)/xENVELOPESPURSIMAGE 0 IMAGE 1 IMAGE 2 IMAGE 3 IMAGE 40–20–40–60–80–100MAGNITUDE(dB

AD9912 Rev. D | Page 19 of 40 SYSCLK INPUTS Functional Description An external time base connects to the AD9912 at the SYSCLK pins to generate the

AD9912 Rev. D | Page 2 of 40 TABLE OF CONTENTS Features ...

AD9912 Rev. D | Page 20 of 40 SYSCLK PLL Multiplier When the SYSCLK PLL multiplier path is employed, the frequency applied to the SYSCLK input pin

AD9912 Rev. D | Page 21 of 40 Note that the SYSCLK PLL bypassed and SYSCLK PLL enabled input paths are internally biased to a dc level of ~1 V. Ca

AD9912 Rev. D | Page 22 of 40 Although the worst spurs tend to be harmonic in origin, the fact that the DAC is part of a sampled system results in

AD9912 Rev. D | Page 23 of 40 THERMAL PERFORMANCE Table 7. Thermal Parameters Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P

AD9912 Rev. D | Page 24 of 40 POWER-UP POWER-ON RESET On initial power-up, the AD9912 internally generates a 75 ns RESET pulse. The pulse is initi

AD9912 Rev. D | Page 25 of 40 POWER SUPPLY PARTITIONING The AD9912 features multiple power supplies, and their power consumption varies with its c

AD9912 Rev. D | Page 26 of 40 SERIAL CONTROL PORT The AD9912 serial control port is a flexible, synchronous, serial communications port that allow

AD9912 Rev. D | Page 27 of 40 Read If the instruction word is for a read operation (I15 = 1), the next N × 8 SCLK cycles clock out the data from t

AD9912 Rev. D | Page 28 of 40 Table 10. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 I14 I13

AD9912 Rev. D | Page 29 of 40 06763-048CSBSCLKSDIOtHIGHtLOWtCLKtStDStDHtHBIT N BIT N + 1 Figure 56. Serial Control Port Timing—Write Table 11. De

AD9912 Rev. D | Page 3 of 40 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, AVS

AD9912 Rev. D | Page 30 of 40 I/O REGISTER MAP All address and bit locations that are left blank in Table 12 are unused. Table 12. Addr (Hex) Typ

AD9912 Rev. D | Page 31 of 40 Addr (Hex) Type1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) Calibration (user-acces

AD9912 Rev. D | Page 32 of 40 I/O REGISTER DESCRIPTIONS SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005) Register 0x0000—Serial Port

AD9912 Rev. D | Page 33 of 40 Register 0x0011—Reserved Register 0x0012—Reset (Autoclearing) To reset the entire chip, the user can use the (non-au

AD9912 Rev. D | Page 34 of 40 CMOS OUTPUT DIVIDER (S-DIVIDER) (REGISTER 0x0100 TO REGISTER 0x0106) Register 0x0100 to Register 0x0103—Reserved Reg

AD9912 Rev. D | Page 35 of 40 Register 0x01A9—FTW0 (Frequency Tuning Word) (Continued) Table 27. Bits Bit Name Description [31:24] FTW0 These

AD9912 Rev. D | Page 36 of 40 DOUBLER AND OUTPUT DRIVERS (REGISTER 0x0200 TO REGISTER 0x0201) Register 0x0200—HSTL Driver Table 32. Bits Bit Nam

AD9912 Rev. D | Page 37 of 40 Register 0x0503—Spur A (Continued) Table 38. Bits Bit Name Description [7:0] Spur A phase Linear offset for Spu

AD9912 Rev. D | Page 38 of 40 OUTLINE DIMENSIONS PIN 1INDICATORTOPVIEW8.75BSC SQ9.00BSC SQ1641617494832330.500.400.300.50 BSC0.20 REF12° MAX0.80 M

AD9912 Rev. D | Page 39 of 40 ORDERING GUIDE Model Temperature Range Package Description Package Option AD9912ABCPZ1, 2 −40°C to +85°C 64-Lea

AD9912 Rev. D | Page 4 of 40 Parameter Min Typ Max Unit Test Conditions/Comments SYSTEM CLOCK INPUT System clock inputs should alway

AD9912 Rev. D | Page 40 of 40 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property

AD9912 Rev. D | Page 5 of 40 AC SPECIFICATIONS fS = 1 GHz, DAC RSET = 10 kΩ, unless otherwise noted. Power supply pins within the range specified

AD9912 Rev. D | Page 6 of 40 Parameter Min Typ Max Unit Test Conditions/Comments CMOS Output Driver (AVDD3/Pin 37) @ 1.8 V Frequenc

AD9912 Rev. D | Page 7 of 40 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Analog Supply Voltage (AVDD) 2 V Digital Supply Voltage (DVDD)

AD9912 Rev. D | Page 8 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1INDICATOR17181920212223242526272829303132NCNCAVDDNCNCNCAVDDAVDDAVDD

AD9912 Rev. D | Page 9 of 40 Pin No. Input/ Output Pin Type Mnemonic Description 32 I 1.8 V CMOS CLKMODESEL Clock Mode Select. Set to GND