Analog Devices AD9883A Instrukcja Użytkownika

REV. 0Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsu

REV. 0AD9883A–10–The PLL characteristics are determined by the loop filter design,by the PLL Charge Pump Current and by the VCO range setting.The loop

REV. 0AD9883A–11–Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display FormatsRefresh HorizontalStandard Resolution Rat

REV. 0AD9883A–12–P0 P1 P2 P3 P4 P5 P6 P75-PIPE DELAYD0 D1 D2 D3 D4 D5 D6 D7RGBINHSYNCPxCKHSADCCKDATACKDOUTAHSOUTVARIABLE DURATIONFigure 8. 4:4:4 Mode

REV. 0AD9883A–13–2-Wire Serial Register MapThe AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An ex

REV. 0AD9883A–14–Table VI. Control Register Map (continued)Write andHex Read or Default RegisterAddress Read Only Bits Value Name Function0FH R/W 7:1

REV. 0AD9883A–15–Table VI. Control Register Map (continued)Write andHex Read or Default RegisterAddress Read Only Bits Value Name Function15H R/W 7:0

REV. 0AD9883A–16–04 7–3 Clock Phase AdjustA 5-bit value that adjusts the sampling phase in 32 stepsacross one pixel time. Each step represents an 11.2

REV. 0AD9883A–17–0E 5 Hsync Output PolarityOne bit that determines the polarity of the Hsync outputand the SOG output. Table XI shows the effect of th

REV. 0AD9883A–18–0F 4 Coast Input Polarity OverrideThis register is used to override the internal circuitry thatdetermines the polarity of the coast s

REV. 0AD9883A–19–13 7-0 Post-CoastThis register allows the coast signal to be applied follow-ing to the Vsync signal. This is necessary in cases where

REV. 0–2–AD9883A–SPECIFICATIONSTest AD9883AKST-110 AD9883AKST-140Parameter Temp Level Min Typ Max Min Typ Max UnitRESOLUTION 8 8 BitsDC ACCURACYDiffer

REV. 0AD9883A–20–Table XXXIV. Detected Coast Input Polarity StatusHsync Polarity Status Result0 Coast Polarity Negative1 Coast Polarity Positive15 7 4

REV. 0AD9883A–21–Data is read from the control registers of the AD9883A in a similarmanner. Reading requires two data transfer operations:The base add

REV. 0AD9883A–22–Table XXXVIII. Control of the Sync Block Muxes via theSerial RegisterControlMux Serial Bus BitNos. Control Bit State Result1 and 2 0E

REV. 0AD9883A–23–It is also recommended to use a single ground plane for the entireboard. Experience has repeatedly shown that the noise perfor-mance

REV. 0–24–C02561–1–10/01(0)PRINTED IN U.S.A.AD9883AOUTLINE DIMENSIONSDimensions shown in inches and (mm).80-Lead LQFP(ST-80)616018020 4121 40TOP VIEW(

REV. 0–3–AD9883ATest AD9883AKST-110 AD9883AKST-140Parameter Temp Level Min Typ Max Min Typ Max UnitDIGITAL OUTPUTSOutput Voltage, High (VOH) Full VI

REV. 0AD9883A–4–CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and

REV. 0–5–AD9883APIN CONFIGURATIONGNDGREEN <7>GREEN <6>GREEN <5>GREEN <4>GREEN <3>GREEN <2>GREEN <1>GREEN <

REV. 0AD9883A–6–PIN FUNCTION DESCRIPTIONSPin Name FunctionOUTPUTSHSOUT Horizontal Sync OutputA reconstructed and phase-aligned version of the Hsync in

REV. 0AD9883A–7–PIN FUNCTION DESCRIPTIONS (continued)Pin Name FunctionCLAMP External Clamp InputThis logic input may be used to define the time during

REV. 0AD9883A–8–At that point the signal should be resistively terminated (75 Ωto the signal ground return) and capacitively coupled to theAD9883A inp

REV. 0AD9883A–9–GAIN1.00.000h FFhINPUT RANGE – Volts0.5OFFSET = 00hOFFSET = 3FhOFFSET = 7FhOFFSET = 00hOFFSET = 7FhOFFSET = 3FhFigure 2. Gain and Offs