Analog Devices ADSP-21020 Instrukcja Użytkownika Pobierz pdf

FUNCTIONAL BLOCK DIAGRAM

EXTERNAL

ADDRESS

BUSES

PROGRAM

SEQUENCER

EXTERNAL

DATA

BUSES

DATA ADDRESS

GENERATORS

DAG 1 DAG 2

PROGRAM MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

DATA MEMORY ADDRESS

INSTRUCTION

CACHE

ARITHMETIC UNITS

SHIFTERMULTIPLIER

ALU

TIMER

JTAG TEST

& EMULATION

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

32/40-Bit IEEE Floating-Point

DSP Microprocessor

ADSP-21020

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 Fax: 617/326-8703

GENERAL DESCRIPTION

The ADSP-21020 is the first member of Analog Devices’ family

of single-chip IEEE floating-point processors optimized for

digital signal processing applications. Its architecture is similar

to that of Analog Devices’ ADSP-2100 family of fixed-point

DSP processors.

Fabricated in a high-speed, low-power CMOS process, the

ADSP-21020 has a 30 ns instruction cycle time. With a high-

performance on-chip instruction cache, the ADSP-21020 can

execute every instruction in a single cycle.

The ADSP-21020 features:

•

Independent Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter

perform single-cycle instructions. The units are architecturally

arranged in parallel, maximizing computational throughput. A

single multifunction instruction executes parallel ALU and

FEATURES

Superscalar IEEE Floating-Point Processor

Off-Chip Harvard Architecture Maximizes Signal

Processing Performance

30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

Execution

100 MFLOPS Peak, 66 MFLOPS Sustained Performance

1024-Point Complex FFT Benchmark: 0.58 ms

Divide (y/x): 180 ns

Inverse Square Root (1/√

x): 270 ns

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats

32-Bit Fixed-Point Formats, Integer and Fractional,

with 80-Bit Accumulators

IEEE Exception Handling with Interrupt on Exception

Three Independent Computation Units: Multiplier,

ALU, and Barrel Shifter

Dual Data Address Generators with Indirect, Immedi-

ate, Modulo, and Bit Reverse Addressing Modes

Two Off-Chip Memory Transfers in Parallel with

Instruction Fetch and Single-Cycle Multiply & ALU

Operations

Multiply with Add & Subtract for FFT Butterfly

Computation

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

Single-Cycle Register File Context Switch

15 (or 25) ns External RAM Access Time for Zero-Wait-

State, 30 (or 40) ns Instruction Execution

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation Circuitry

223-Pin PGA Package (Ceramic)

multiplier operations. These computation units support IEEE

32-bit single-precision floating-point, extended precision

40-bit floating-point, and 32-bit fixed-point data formats.

•

Data Register File

A general-purpose data register file is used for transferring

data between the computation units and the data buses, and

for storing intermediate results. This 10-port (16-register)

architecture, allows unconstrained data flow between

computation units and off-chip memory.

•

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-21020 uses a modified Harvard architecture in

which data memory stores data and program memory stores

both instructions and data. Because of its separate program

and data memory buses and on-chip instruction cache, the

processor can simultaneously fetch an operand from data

memory, an operand from program memory, and an

instruction from the cache, all in a single cycle.

•

Memory Interface

Addressing of external memory devices by the ADSP-21020 is

facilitated by on-chip decoding of high-order address lines to

generate memory bank select signals. Separate control lines

are also generated for simplified addressing of page-mode

DRAM.

The ADSP-21020 provides programmable memory wait

states, and external memory acknowledge controls allow

interfacing to peripheral devices with variable access times.

1 2 3 4 5 6 ... 31 32

Podsumowanie treści

Strona 1 - ADSP-21020

FUNCTIONAL BLOCK DIAGRAMEXTERNALADDRESSBUSESPROGRAMSEQUENCEREXTERNALDATABUSESDATA ADDRESSGENERATORSDAG 1 DAG 2PROGRAM MEMORY ADDRESSPROGRAM MEMORY DAT

Strona 2

ADSP-21020REV. C–10–Table V. Multiplier Compute OperationsRn = Rx * Ry ( SSF ) Fn = Fx * FyMRF = Rx * Ry ( UUIMRB = Rx * Ry (U U FRRn = MRF + Rx * Ry

Strona 3

ADSP-21020REV. C–11–Table Vll. Multifunction Compute OperationsFixed-PointRm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R1

Strona 4

RECOMMENDED OPERATING CONDITIONS K Grade B Grade T Grade Parameter Min Max Min Max Min Max UnitVDDSupply Voltage 4.50 5.50 4.50 5.50 4.50

Strona 5

ADSP-21020REV. C–13–TIMING PARAMETERSGeneral NotesSee Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do no

Strona 6

ADSP-21020REV. C–14–InterruptsK/B/T Grade K/B/T Grade B/T Grade K Grade20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency* Parameter Min Max Min Max M

Strona 7

ADSP-21020REV. C–15–FlagsK/B/T Grade K/B/T Grade B/T Grade K Grade20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*Parameter Min Max Min Max Min Ma

Strona 8

ADSP-21020REV. C–16–Bus Request/Bus GrantK/B/T Grade K/B/T Grade B/T Grade K Grade20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*Parameter Min Max

Strona 9

ADSP-21020REV. C–17–External Memory Three-State ControlK/B/T Grade K/B/T Grade B/T Grade K Grade20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*Par

Strona 10

ADSP-21020REV. C–18–Memory ReadK/B/T Grade K/B/T Grade B/T Grade K Grade20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence*Parameter Min Max Min Max M

Strona 11

ADSP-21020REV. C–19–CLKINDATADMACK,PMACKADDRESS,SELECTDMPAGE,PMPAGEtDARLtDAPtDAAKtDCKRLtDRAKtSAKtHAKtDADtDRLDtRWRtHDRHtRWtHDADMWR,PMWRDMRD, PMRDFigure

Strona 12 - ADSP-21020–SPECIFICATIONS

ADSP-21020REV. C–2–•Instruction CacheThe ADSP-21020 includes a high performance instructioncache that enables three-bus operation for fetching aninstr

Strona 13

ADSP-21020REV. C–20–Memory WriteK/B/T Grade K/B/T Grade B/T Grade K Grade20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*Parameter Min Max Min Max

Strona 14

ADSP-21020REV. C–21–CLKINDATADMACK,PMACKADDRESS,SELECTDMPAGE,PMPAGEtDAWLtDAPtDAAKtDCKWLtDWAKtSAKtHAKtWDEtDWHAtWWRtDDWRtDDWHtWWtDAWHtHDWHDMWR,PMWRDMRD,

Strona 15

ADSP-21020REV. C–22–IEEE 1149.1 Test Access PortK/B/T Grade K/B/T Grade B/T Grade K Grade20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*Parameter

Strona 16

ADSP-21020REV. C–23–TCKTMS,TDITDOSYSTEMINPUTSSYSTEMOUTPUTStSTAPtHTAPtDTDOtSSYStHSYStDSYStTCKFigure 12. IEEE 1149.1 Test Access Port

Strona 17

ADSP-21020REV. C–24–TEST CONDITIONSOutput Disable TimeOutput pins are considered to be disabled when they stopdriving, go into a high-impedance state,

Strona 18

ADSP-21020REV. C–25–Capacitive LoadingOutput delays are based on standard capacitive loads: 100 pFon address, select, page and strobe pins, and 50 pF

Strona 19

ADSP-21020REV. C–26–ENVIRONMENTAL CONDITIONSThe ADSP-21020 is available in a Ceramic Pin Grid Array(CPGA). The package uses a cavity-down configuratio

Strona 20

ADSP-21020REV. C–27–All GND pins should have a low impedance path to ground. Aground plane is required in ADSP-21020 systems to reduce thisimpedance,

Strona 21

ADSP-21020REV. C–28–TCKPMA21PMPAGETRSTRCOMPDMACKTDODMTSPMWRPMD47PMD46PMD44PMD42PMD41PMD38DMD22EVDDDMD24DMD25DMD26DMD23DMD27DMD28DMD33DMD29DMD35DMD36DM

Strona 22

ADSP-21020REV. C–29–DMD7 DMD8 DMA14 DMA13DMD12 DMD14 DMD18 DMD21DMD22DMD26 DMD32 DMD33 DMD37 DMD39 DMA21 DMA17 DMA16EVDD DMD23 DMD29 DMD34 DMA22BGBRBO

Strona 23

ADSP-21020REV. C–3–the standard IEEE format, whereas the 40-bit IEEE extended-precision format has eight additional LSBs of mantissa forgreater accura

Strona 24

ADSP-21020REV. C–30–PGA PIN PGA PIN PGA PIN PGA PINLOCATION NAME LOCATION NAME LOCATION NAME LOCATION NAMEG16 DMA0 B5 DMD25 K1 PMD9 L16 TIMEXPG17 DMA1

Strona 25

ADSP-21020REV. C–31–OUTLINE DIMENSIONSDimensions shown in inches and (mm).223-Pin Ceramic Pin Grid ArrayDDAA1L3b1φehbφj1j2ABCDEFGHJ KLMNPRSTU123456789

Strona 26

ADSP-21020REV. C–32–C1601c–5–8/94PRINTED IN U.S.A.ORDERING GUIDEAmbient Temperature Instruction Cycle TimePart Number* Range Rate (MHz) (ns) PackageAD

Strona 27

ADSP-21020REV. C–4–in a specified register, either before (premodify) or after(postmodify) the access. To implement automatic moduloaddressing for cir

Strona 28

ADSP-21020REV. C–5–41×CLOCKCLKINPMAPMDDMACKDMADMDADSP-21010244832322PMACK4DMPAGEPMPAGEFLAG3-0JTAG54RCOMPTIMEXPADDRDATAPROGRAMMEMORYSELECTSOEWEPMS1-0PM

Strona 29

ADSP-21020REV. C–6–PinName Type FunctionDMPAGE O Data Memory Page Boundary. The ADSP-21020 asserts this pin to signal that a datamemory page boundary

Strona 30

ADSP-21020REV. C–7–COMPUTE AND MOVE OR MODIFY INSTRUCTIONS1. compute,|DM(Ia, Mb) = dreg1|,|PM(Ic, Md) = dreg2|;|dreg1 = DM(Ia, Mb)||dreg2 = PM(Ic, Md)

Strona 31

ADSP-21020REV. C–8–Table II. Condition and Termination CodesName Descriptioneq ALU equal to zerone ALU not equal to zeroge ALU greater than or equal t

Strona 32

ADSP-21020REV. C–9–Table III. Universal RegistersName FunctionRegister FileR15–R0 Register file locationsProgram SequencerPC* Program counter; address

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